This invention relates generally to a semiconductor integrated circuit structure and method of making the same and more particularly to such structures in which the implanted dimensions are maintained during annealing whereby to permit the formation of microgeometry transistors and semiconductor integrated circuits.
In the formation of integrated circuit structures it is desirable to reduce the size of the structure as much as possible. Reduction in size reduces the amount of surface area which is required to form integrated circuits whereby more junctions can be placed on a single semiconductor chip. Furthermore, the reduction in size permits operation at much higher frequencies.
Reference is made to FIGS. 1 and 2 to illustrate the general problem encountered with present day process. FIG. 1 is a schematic illustration of an idealized n-channel MOSFET which can be incorporated in an integrated circuit. This device includes a p-type substrate 11 having heavily doped n-type (n.sup.+) inset regions 12 and 13 forming source and drain contact wells. The wells are separated from each other by a distance L.sub.G. The source and drain wells are taken to be identical and have a width Z and a length L. An oxide 14 and a thin metal layer 16 called the gate are fabricated over the region separating the source and drain and provide the control feature for the device. Metal source and drain contacts 17 and 18 overlie the oxide 14 and contact the wells 12 and 13. Briefly, an n-type conducting channel, shown in dotted line in FIG. 1, can be formed between the source and drain by applying a sufficiently large voltage between the gate and the source or the gate and the substrate. Current can then flow from the drain through the channel to the source. The presence or absence of a conducting channel provides the ON-OFF characteristic required for operation of the device in digital electronic circuits.
Referring to FIG. 2, it is seen that the minimum surface area of the active device is A=Z (2L+L.sub.G). The gate length L.sub.G is generally essentially equal to the length of the source and drain contact wells and the area A is then approximately equal to 3ZL.
From these geometrical considerations it is seen that, for a given value of Z, devices of small area require small values of L. Hence, the number of devices that can be placed on a given area of a silicon integrated circuit depends on how small L can be made.
The maximum operating frequency for the device depends of L.sub.G through the approximate formula ##EQU1## where .mu. is the carrier mobility in the channel, V.sub.GS is the applied voltage between gate and source and V.sub.T is the voltage that must be applied to form the conducting channel. It will be apparent from Eq.(1) that small values of L.sub.G give large values of f. Hence, for both high packing density (small device area) and high speed of operation, L must be made as small as possible.
Currently values of L in the range of 1-2 .mu.m represent practical limits of fabrication. The reason for this is illustrated in FIG. 3. FIG. 3 shows a single MOS device in which the source and drain contact wells 12 and 13 have been prepared by solid state diffusion. In this process, an oxide 14 is first grown on the semiconductor after which holes 19 are cut in the oxide by a process called photoengraving to expose the semiconductor. An n-type dopant such as phosphorus is then diffused through the holes 19 into the silicon by techniques well known to those skilled in the art. The diffusing phosphorus penetrates a depth D into the semiconductor and also moves a distance D laterally underneath the oxide. This lateral movement is critical since it cannot be permitted to proceed to the point where the source and drain contact wells touch each other. In fact, for reliable device operation, it is customary to limit the lateral penetration to D.ltorsim.0.1 L.sub.G.
This lateral penetration phenomenon becomes critical when the dimensions of the device are reduced in an effort to increase the device packing density in an integrated circuit. For example, in order to introduce enough dopant into the semiconductor to form satisfactory n.sup.+ wells, it is necessary to perform the diffusion under conditions such that the diffusion depth D will be at least 0.5 .mu.M. The lateral penetration will, therefore, also be 0.5 .mu.m, and therefore the gate length must be on the order of 5 .mu.m. A single device having Z=100 .mu.m will then occupy an area of approximately 3.times.100 .mu.m.times.15 .mu.m or 4500 (.mu.m).sup.2.
While this is satisfactory for many applications, photoengraving techniques that employ scanning electron beams or x-rays are capable of producing openings in the oxide that provide L.ltorsim.0.1 .mu.m. Hence the basic device length can be reduced by more than an order of magnitude if a reliable procedure can be found for producing source and drain contact wells in closely-spaced regions.
The lateral penetration phenomenon just discussed makes solid state diffusion a poor candidate for fabrication of such small devices simply because the source and drain wells will diffuse into contact before sufficient doping has been introduced to make satisfactory wells.
A procedure that can be used to avoid part of this problem is to use ion implantation to introduce the dopant into the source and drain contact wells. Such a procedure is illustrated schematically in FIG. 4, where the semiconductor wafer 21 is exposed to a phosphorus ion beam 22. The photoresist 23 left on top of the oxide is one of many procedures known to those skilled in the art that can be used to prevent the beam from reaching the semiconductor or the oxide 24 where doping is to be avoided.
The implantation process provides essentially square contact wells 26. However, the ion beam also produces significant damage in the semiconductor, and this damage must be annealed before the doping characteristics of the implanted ions can be realized. The annealing can be carried out by placing the implanted sample in an annealing furnace. However, the implanted impurities diffuse during this annealing cycle, and hence the lateral penetration problem is once again made manifest, as illustrated in FIG. 5 by the region 27.
Referring to FIG. 6 which shows the impurity profile of an implanted species both before and after annealing, the profile prior to annealing is shown by the squares. The triangles show the profile after thermal annealing. It is seen that thermal annealing has produced a redistribution. In particular, the thermally annealed impurity distribution is now deeper than the as-implanted distribution. This increase in depth would be matched by a comparable lateral penetration if the dopant had been introduced through oxide windows into the silicon.
The use of laser energy to cause diffusion and annealing of implanted arsenic in silicon is taught by G. A. Kachurin and E. V. Nideav, Soviet Phys. Semiconductors, Vol. 11 No. 3 March 1977. They teach use of a ruby laser with energy density in the range of 90 Joules/cm.sup.2 to cause substantial diffusion of implanted arsenic in silicon.
There is a need for a process and structure in which the extent of the inset regions is determined by the size of the openings or windows and the depth of ion implantation.